Hi, we have many years experience working with Xilinx/Altera FPGA and Verilog/VHDL programing languages. We can surely help you solve the problem.
Could you please share more details about your issue? What is your problem: Compilation error or synthesis error or wrong result when running simulation or wrong result when running on real FPGA? How are you sure that the problem come from MAC unit design? More information is preferable so that we can help you in detail.
Thanks,