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    3,151 fpga design mississauga jobs found, pricing in USD
    from C++ to openCL 6 days left
    VERIFIED

    Need to convert some specific loops in a C++ code to OPENCL for execution on FPGA

    $22 (Avg Bid)
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    We are looking for a Matlab & simulink expert for modelling FPGA in Xilinx vivado. The project will be a part of training on simulink for 8 hours.

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    I am in need of a Verilog programmer. I have a circuit with an FPGA daughterboard (Digilent Cmod A7-35T) that connects to a DAC. I need some code developed for this setup. Right now the FPGA has working firmware that does simple ramp generation. This code is most likely simple enough that you can use it to easily figure out how to write to the DAC. There's a newer version of the firmware th...

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    The objective of this project is to 1) write a PCIe Driver for a FPGA card to communicate with motherboard PCIe. 2) Two Interrupt Service Routine (one for the FPGA Card and one for the Host PC all in Linux environment

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    VHDl Based design 5 days left
    VERIFIED

    ADS7038 Xilinx Virtex DAC7750 If 1Vpp is given to ADS7038 it should convert that input into digital signal and store it into the memory of Xilinx Virtex FPGA and DAC7750 should convert the digital stored data into analog 1Vpp. Write VHDL code for communication with ADS7038 and DAC7750 where FPGA Virtex is the master controller. Write the code on Xilinx Vivado and send simulation pictures. The c...

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    Job Description :- 1) Go through the PCIe Gen Spec and understand the requirement of 8b/10b Encoder/Decoder and Scrambler/Descrambler 2) Create a Perl-Automated Verilog Code of 8b/10b Encoder/Decoder and Scrambler/Descrambler. In the scrambler, polynomial should be a variable that is passed on from Perl domain to generate Various Verilog Code for Gen3/Gen4/Gen5 Required Scrambler/Descrambler. 3) ...

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    Modulation and Demodulation of QPSK using VHDL using XILINX IDE.

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    We are looking for a Matlab FPGA expert with hands on experience on xlinix Arty A7 100T board for an eight hour training covering connecting sensors and verilog coding.

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    We are looking for an expert in Matlab for calculating PTT using ECG & PPG signals and moving it into an FPGA board.

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    The project is based on designing of automotive radar system using matlab simulink block and to perform speed, distance, angle of azimuth and angle of elevation estimatioin and then performing high level synthesis to generate RTL code of design using Matlab HDL coder [login to view URL] of different parameters like speed and distance using HLS directives of generated HDL code . Implementation an...

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    I have to 3D acoustic SSL using Matlab(GCC-PHAT)+FPGA+Labview+ARM(STM32).

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    Use Xilinx IDE to create the project. More details can be provided.

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    Hi Islam M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Implementing the NDI protocol on an MCU or FPGA specifically for audio purposes.A full SDK is available It's mainly implementation that can be done on a development board. SDK is available here [login to view URL] Ability to send and receive audio channels at various sample rates and TDM or I2S interface. The unit would have an Ethernet interface transporting the protocol and then connects ...

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    19 bids

    This project is based on design and implementation of FMCW automotive radar system on Matlab Simulink and calculation of different parameter like speed ,distance and angle and converting signal processing block of radar system into HDL code and verifying the same scenario with same input. Later, optimization of generated HDL code and implementing HDL code into FPGA and verifying it with same inpu...

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    Hi, I need some help with an initial detailed feasibility study on how to Port Micropython onto an open-source RISC V SoC ( i will send you the exact CPU implementation at a later stage) running on Arty A7 35T FPGA board and how much work is involved with a detailed task list and an estimated timescale. The projects end goal is to build RISC V porting with all the GPIO & peripherals working ...

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    The project is based on designing of automotive radar system using Matlab Simulink block and to perform speed, distance, angle of azimuth and angle of elevation estimation and then performing high level synthesis to generate RTL code of design using Matlab HDL coder tool. Optimization of different parameters like speed and distance using HLS directives of generated HDL code . Implementation and ve...

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    The project I’m working on is called Dust Detection on Reed Switch Images. The project is implemented on the Zynq device on a custom FPGA development board. The first half of the algorithm is implemented on the PL side (using Vivado HLS and IDE) and the second half of the project is to be implemented on the PS side of the Zynq device (using Xilinx SDK). The steps that are to be implemen...

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    Hello How are you? I have python code for drawing similar to cyclone. I need FPGA code that can draw exactly the same thing. Desired image and python file is attached. Who can help me. Please place "Cyclone" on your header of bid. Thanks

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    I'm looking for an RF engineer to design a high performance RF receiver. The end product will be a commercially available radar detector, able to warn drivers of upcoming speed traps. Competitive advantage will be tied into the electrical performance, so it must be able to outperform all products on the market. The objective of this to produce an approach that meets all performance requirem...

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    I need to help to design Arbiter PUF and Ring Oscillator PUF and implement it in FPGA and writing in Verilog HDL then writing MATLAB code to simulate The PUFs and get results

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    • All the coursework has to be done in VHDL. Coursework handed in using another language will be marked as zero. • Coursework must be typeset. • Never use screenshots or photograph of code in your coursework. Typeset code within your coursework report using a monospace font (e.g. courier new). • Never use photographs of waveforms in your coursework. Use a proper screen capture ...

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    I need some one very good in vhdl,fpga and CAO for a project

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    FPGA Application Project, guidance on PL to PS communication logic.

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    I would like to start this project by having a long tutoring sessions in SoC FPGA with DNN knowledge to implement the algorithm and optimize them. Basically, you should have been working with Xilinx board SoC FPGA, accelerator design, coding in HLS, Vitis. Being able to build ANN like CNN, LSTM, RNN, GANs, with Pytorch or Tensorflow and optimize them using deep compression, pruning, and quantizati...

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    Design and implementation of PUF in FPGA and simulate in MATLAB

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    Taking the measurements and preparing architectural and structural as built drawings for a two storey building in Mississauga ontario

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    This is Nada Eissa, HR Generalist at LxT; a service provider for AI/ML companies. We currently have a project in Mississauga, Ontario and we need your consultation concerning recruitment there (salary structure, contracts... etc). If you're available and interested, we can manage a meeting together. PS: You should be Ontario resident

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    Hi, I hope you are well. I need to replicate the project available here: [login to view URL] on the ZCU102 board. Note that all files are available, and I will provide the ZCU102 constraints. The goal is to have it running using the OpenOCD. Please message me for more information.

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    The project is based on designing of automotive radar system using matlab simulink block and to perform speed, distance, angle of azimuth and angle of elevation estimatioin and then performing high level synthesis to generate RTL code of design using Matlab HDL coder [login to view URL] of different parameters like speed and distance using HLS directives of generated HDL code . Implementation an...

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    Hi Duc D., I was wondering if you could help me with the following project https://www.fr.freelancer.com/projects/fpga/system-verilog-alarm-clock-lite/?ngsw-bypass=&w=f

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    I am looking for a programmer expert in VHDL and FPGA programming. I have the code for the integration of OVG760 camera with the microcontroller (BASYS 3) and I also have the UART code(Serial Data transmission). I need someone to help me integrate both codes so that I can take a picture from OVG760 camera and using UART transfer it to PC. Budget will be discussed later

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    Need a design on FPGA for identifying the cordinate of a object moving on a conveyor and send the data via serial port using vision camera

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    https://www.fr.freelancer.com/projects/fpga/system-verilog-alarm-clock-lite/?ngsw-bypass=&w=f Hello , can I aask you for help with this project?

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    We are a US based robotics company who are designing an AI project that will be based on the Xilinx Kria SOM. We are looking for assistance in the development of firmware / software. Experience with Ultrascale FPGA families and associated tools (Vivado, Vitis, Petalinux) needed.

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    I need to design a digital watch circuit using Verilog/VHDL.: A BCP for FPGA(IC), the schematic of the clock, Verilog/VHDL code, and a report about them

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    prepare a I2C module for Altera FPGA

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    Alarm clock for a DE10-Lite for listed specs.

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    I'm looking for a FPGA / Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The board is a Zedboard (Z7020) connecting to the RF front-end (MAX2771 EK). The project consists of -) Creating in baremetal application a Vivado pipeline (2019.1) to collect RF data from the MAX2771 to be transferred to the FPGA side of the Zynq SoC -) Optimise our code for GPS posi...

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    FIR filter has a number of useful properties compared to an IIR filter i.e. inherently stable, no feedback require, designed to be linear [login to view URL] Impulse response (FIR) with low cost and high performance and its its implementation using various algorithm may be extended for observation of an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e....

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    Design Specifications for the Alarm Clock ▪ Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23). o Whenever the ...

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    I want to create multiple business locations at various cities in Ontario, Canada. I can provide my services at entire province but I don't have the physical location available at each city. So how to avail Google my business listing for each city separately? Requirements: 1. Create multiple Google my business listings through auto verification method. 2. New listings must get auto verified ...

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    Hi Duc D., I noticed your profile and I saw that you had written an alarm clock program for an DE10-Lite FPGA in verilog. If you still have a copy of the code I would like to purchase it from you.

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    Development of existing VHDL design in Quartus, targeting a Cyclone IV chip. It has a functioning PCIe interface. The design takes 12 channels of 10MHz ADC data from optical detectors. There is a need for additional pulse analysis functionality and to address a bug in an output derived from a combination of the 12 data channels.

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    I need some one write veriloge code for pan tompkins algorithm to detect ECG QRS, Bpm , Heart rate , contact ECG sensor with FPGA zybo

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    I look forward to moving our work over onto the freelancer platform. I will send design requirements.

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    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

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    Hi, i have this coding about image processing using verilog that i took from here [login to view URL] but i have a problem trying to make it synthesizable. Can you help me with that?

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    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

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    I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [login to view URL] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for bcu and 650 for cvp I pay you 250 € after successful test From my experience guys are taking a pc miner version that exist...

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