Parameterized Mux (one hot) and (priority coded) System Verilog (Synthesizable)

Completed Posted 5 years ago Paid on delivery
Completed Paid on delivery

Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

Electrical Engineering Electronics Engineering FPGA Verilog / VHDL

Project ID: #18660194

About the project

2 proposals Remote project Active 5 years ago

Awarded to:

raulbehl

Hello jonathanrossy! Please check my profile and reviews to know more about me and my work. It would be great if I could help you out. PS: We have worked on a couple of such projects in the past as well. Thank More

$40 USD in 1 day
(87 Reviews)
6.3

2 freelancers are bidding on average $95 for this job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using system verilog please check my profile also please message me so that we can discuss

$150 USD in 1 day
(502 Reviews)
8.1