1. Write a Verilog model of a synchronous finite state machine whose output is the sequence 0, 2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count when Run is re-asserted. Clearly state any assumptions that you make.
2. Write a Verilog model of the Mealy FSM described by the state diagram in Fig. P5.48. Develop a test bench and demonstrate that the machine state transitions and output correspond to its state diagram.
3. Draw the state diagram of the machine described by the Verilog model given below.
module Prob_5_52 ( output reg y_out, input x_in, clk, reset);
parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;
reg [1:0] state, next_state;
always @ ( posedge clk, negedge reset) begin
if (reset == 1'b0) state <= s0; else state <= next_state;
always @(state, x_in) begin
y_out = 0; next_state = s0;
s0: if x_in = 1 begin y_out = 0; if (x_in) next_state = s1; else next_state = s0; end
s1: if x_in = 1 begin y_out = 0; if (x_in) next_state = s2; else next_state = s1; end
s2: if x_in = 1 if (x_in) begin next_state = s3; y_out = 0; else begin next_state = s2; y_out = 1; end
s3: if x_in = 1 begin y_out = 1; if (x_in) next_state = s0; else next_state = s3; end
default : next_state = s0;
4. Develop the state diagram for a Mealy state machine that detects a sequence of three or more consecutive 1's in a string of bits coming through an input line. Write and verify a Verilog behavioral model of the counter designed
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