# Verilog for beginers

Budget $10-30 USD

- Freelancer
- Jobs
- Verilog / VHDL
- Verilog for beginers

1. Write a Verilog model of a synchronous finite state machine whose output is the sequence 0, 2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count when Run is re-asserted. Clearly state any assumptions that you make.

2. Write a Verilog model of the Mealy FSM described by the state diagram in Fig. P5.48. Develop a test bench and demonstrate that the machine state transitions and output correspond to its state diagram.

3. Draw the state diagram of the machine described by the Verilog model given below.

module Prob_5_52 ( output reg y_out, input x_in, clk, reset);

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11;

reg [1:0] state, next_state;

always @ ( posedge clk, negedge reset) begin

if (reset == 1'b0) state <= s0; else state <= next_state;

always @(state, x_in) begin

y_out = 0; next_state = s0;

case (state)

s0: if x_in = 1 begin y_out = 0; if (x_in) next_state = s1; else next_state = s0; end

s1: if x_in = 1 begin y_out = 0; if (x_in) next_state = s2; else next_state = s1; end

s2: if x_in = 1 if (x_in) begin next_state = s3; y_out = 0; else begin next_state = s2; y_out = 1; end

s3: if x_in = 1 begin y_out = 1; if (x_in) next_state = s0; else next_state = s3; end

default : next_state = s0;

endcase

end

endmodule

4. Develop the state diagram for a Mealy state machine that detects a sequence of three or more consecutive 1's in a string of bits coming through an input line. Write and verify a Verilog behavioral model of the counter designed

## 7 freelancers are bidding on average $27 for this job

Dear sir I have more than 8 years experience in digital design using verilog I read the attachment and I am very interested in working on it please message me so that we can discuss

Hi, I had several years of experience in FPGAs and Verilog HDL, VHDL. I can easily do this project for you. I can deliver this project in 1 day. Kind Regards,

I am an Electrical Engineer having specialization in Electronics and Control, working as Lab Engineer at FAST National University Pakistan, at Electrical Department. Now a days i am also doing my MS degree in Electrica More

Exper in verilog......................................................................................................................................

Hi I am an electrical engineer and a lecturer in a reputed university. I do experience in such tasks. I can help you better. Award me the project and get it done in a best way.. Thanks