MATRIX MULTIPLICATION USING SYSTOLIC ARCHITECTURE IN VERILOG in 10 hr

Your creative pursuits are my most exciting endeavors! This is because I am a passionate, creative, and committed professional and consultant. You have big decisions to make in your hiring process and I welcome all questions you have for me. The best projects are the ones where my clients and I are on the same page before we start so the creative energy can start to flow. Contact me for Regardless of the size of a project, if I am involved, I am committed to its quality and integrity. ACADEMIC QUALIFICATIONS  MSC in Telecommunications (2008 – 2014) o Networking & Data Communications – Routing protocols OSPF & BGP, MPLS and Network design (WAN, MAN, LAN) o Telecommunication Networks – GSM/GPRS/EDGE, IMS/WiMax, WLAN, WCDMA/HSPA, CDMA2000 o Traffic Engineering – Internet Traffic (Web, FTP, Telnet, SNMP & SMTP) modeling, Router design & Queue estimation  BSc Engineering honors degree in Electronics and Telecommunications Engineering (2000-2004) – Majoring Electronics and Telecommunications.

I have been working on it.I almost have it... well at least in VHDL. I admit it's been a tough cookie! :P Why do you want it in 10 hours?

I have 5 years experience in digital circuit design using FPGA and I complete a lot of projects using Verilog. And I implement a lot of circuits using Altera and Xilinx FPGAs. I already finish your required project and you can see the simulation photos of the project on my profile in my portfolios. I complete this project by $70 but This my first project on freelancer.com so I bid this project only by 650 INR.

I can give the verilog code for 3x3 matrix multiplication using Systolic 2D grid implementation. I am not sure what your requirement is. If your requirement is different then please specify it explicitly.