Design two basic digital logic gates NAND and NOR and compare/discuss their power characteristics versus performance when scaling down from 45nm to 32nm technologies.

1. For each gate draw the schematics showing the internal MOSFETs and connections, and create the corresponding HSPICE decks for: • 3-input NAND gate • 3-input NOR gate 2. Simulate the functionality of the above gates for all input combinations using HSPICE and Cosmo Scope. 3. For each NAND and NOR gate determine the followings using 45nm and 32nm technology nodes: • The worst-case delay from input to output • The dynamic power dissipation • The static power dissipation 4. Your report must include: i. The truth table of the NAND and NOR circuits (2 truth tables total) ii. The internal circuit schematic diagram showing the MOSFETs, connections, input , output, and power supply pins (2 schematics total) iii. The SPICE decks for the NAND and NOR circuits (Total of 8 SPICE decks: 1 for 45nm NAND static power, 1 for 45nm NAND dynamic power, 1 for 32nm NAND static power, 1 for 32nm NAND dynamic power, 1 for 45nm NOR static power, 1 for 45nm NOR dynamic power, 1 for 32nm NOR static power, 1 for 32nm NOR dynamic power) iv. Cosmo Scope wave forms for all input combinations with their corresponding outputs. v. Eight portion of the .lis file corresponding to each of the SPICE decks that shows the values obtained for dynamic and static power in each case (do not print the entire .lis file for each case). vi. Your observations and conclusions, emphasizing on the trends observed when the technology node is scaled down from 45nm to 32nm.