FPGA-Xilinx-VHDL Angle detect

**Add to an existing FPGA project two new functionality.** Programming environment: Xilinx ISE 11.2 Xilinx device: XC3S700AN Simulator is required to check design Phase angle: Calculate the angle between three analogue signals of a three phase power system namely phase 1, 2 and 3. The code for sampling the signals are already implemented. The signal need to be filtered. The calculated angles (2) will be between phase 1&2 and phase1&3. A technical article is available to implement the solution. GPS time stamp: A PPS (pulse per second) signal is available and a 10Mhz clock is available at two I/O pin of the FPGA. A 24 bit counter (GPS counter) will be incorporated into the FPGA, clocked by the 10 MHz clock and reset by the PPS. When the phase voltages crosses zero, the content of the GPS counter is transfer into a corresponding register to be transfer to a microcontroler. ## Deliverables The programming language must be VHDL.