Xilinx FPGA Camera Pipeline -- 2

Create a time-synchronized stereo pair of cameras with four virtual devices. Each camera should support 4K @ 60 FPS and 1080P @ 240 FPS using the Jetson ISP and nvBuffers / libargus. 240hz camera to support monochrome image capture. One camera will need to be able to capture near IR. The low-res image-streams can be grey-scale; one of the high-res cameras can be grey-scale.

Enable a camera system that can capture synchronized high bandwidth data from a CMOS sensor via LVDS to MIPI enabled FPGA that mounts camera devices on the Xavier AGX platform using Jetson ISP and a GeoSEMI ISP. Develop Tegra driver to capture data using GeoSEMI ISP and the Jetson ISP and modify device tree to mount the camera into the userspace. Developer Xavier AGX daughterboard to have 2 LVDS inputs for dual GPixel GMAX2509 sensors with GeoSEMI ISP and 4 MIPI outputs with 4x CSI lanes. Use Xilinx FPGA co-mounted on daughterboard to capture, convert and send data to the Xavier AGX platform by converting LVDS input to DSI output. Use DSI output routed via PCB traces to integrate with the AGX Xavier camera connector.

Linux Verilog / VHDL PCB Layout FPGA Embedded Systems

Project ID: #31180631

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