This project requires you to develop a high-speed FPGA design for integer division. Only those who have experience in Matlab, SIMULINK, XILINX and SYSTEM GENERATOR the apply. Otherwise please don't. Deadline is Monday. I'll provide the template and algorithm and implementation process.
## Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or 10 64-bit are the assumed platform.