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VLSI Design Engineer - Part Time

₹1500-12500 INR

Closed
Posted over 5 years ago

₹1500-12500 INR

Paid on delivery
Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.
Project ID: 17806356

About the project

9 proposals
Remote project
Active 5 yrs ago

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9 freelancers are bidding on average ₹9,527 INR for this job
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Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
₹13,888 INR in 3 days
4.9 (94 reviews)
6.9
6.9
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Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.
₹12,500 INR in 7 days
4.9 (83 reviews)
6.3
6.3
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Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS, modelsim, vivado FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip with 16 core of 16bit MIPS such that I think I can do your task very well. Best Regard.
₹1,500 INR in 3 days
5.0 (8 reviews)
4.2
4.2
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Hi, I have done my Mtech in VLSI design. I had also done my thesis on FPGA implementation of multiplier using verilog on Xillinx. please give me one chance.
₹13,888 INR in 7 days
0.0 (0 reviews)
0.0
0.0
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Currently working in Qualcomm. This maybe my first project in Freelancer, so im giving you very cheap quote.
₹7,777 INR in 3 days
0.0 (0 reviews)
0.0
0.0
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Has 3yr of experience in RTL design and Test bench writing in VHDL/ Verilog/ System verilog . Handled many FPGA related project from RTL design( in both Verilog/VHDL) to bring up . worked on : UART,I2C,SPI,Ethernet(RGMII,XGMII),DDR3,DAC,SERDES.. Thank you.
₹11,111 INR in 3 days
0.0 (0 reviews)
4.4
4.4
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Hi, I can give guarantee of my work. I put 100% in my work.
₹10,000 INR in 7 days
0.0 (0 reviews)
0.0
0.0

About the client

Flag of INDIA
Bengaluru, India
0.0
0
Member since Sep 20, 2018

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