VHDL - Design Programming and Simulation Test Bench

General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall be used to initialize the design (BTNC button on the Basys3 board). The whole design uses a 100 MHz clock. One switch for the selection of the count direction (CNT_UP/CNT_DOWN). ‘1’ … count up, ‘0’ … count down. If the counter reaches the maximum value (minimum value in case of count down) it continues counting at the minimum value (maximum value in case of count down). One switch for holding the counter (CNT_HOLD) ‘1’ … hold, ‘0’ … normal operation. One switch for resetting the counter (CNT_RESET) ‘1’ … reset, ‘0’ … normal operation The priorities for these switches are: 1. reset 2. hold 3. count direction The counting mode (decimal, hexadecimal, or octal) and the counting frequency of the least significant digit (1 Hz, 10 Hz, 100 Hz, or 1000 Hz) depend on your number in the attendance list as shown in Table 1 (if you work in groups, use the number of the group member with the lowest number). All four digits of the counter have to count at the same clock edge, this has to be proven by simulation.