A synthesizable implementation of Compression engines
Cancelled
Posted
Mar 7, 2012
Paid on delivery
$30-250 USD
Paid on delivery
Cancelled
Paid on delivery
The implementation may be a mixed HW-SW approach.
May include multiple implementations, codes or algorithms.
Use data in block sizes of 512B, 1K, 2K, 4K
Memory input/output in 8, 16, 32 or 64 bits. Engine input/output left up to implementer
Clock of at least 50MHz (if using 90nm library)
The implementation may be a mixed HW-SW approach.
More information will be provided to bidders.
Project ID: #1489354
About the project
4 proposals
Remote project
Active Mar 15, 2012
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