A synthesizable implementation of Compression engines

Cancelled Posted Mar 7, 2012 Paid on delivery
Cancelled Paid on delivery

The implementation may be a mixed HW-SW approach.

May include multiple implementations, codes or algorithms.

Use data in block sizes of 512B, 1K, 2K, 4K

Memory input/output in 8, 16, 32 or 64 bits. Engine input/output left up to implementer

Clock of at least 50MHz (if using 90nm library)

The implementation may be a mixed HW-SW approach.

More information will be provided to bidders.

Electrical Engineering Electronics Engineering Matlab and Mathematica Verilog / VHDL

Project ID: #1489354

About the project

4 proposals Remote project Active Mar 15, 2012

4 freelancers are bidding on average $275 for this job

bchandra1955

Professional CS engineer from academic institute can take care

$330 USD in 15 days
(50 Reviews)
5.5
reallifetech

See details in MB.

$220 USD in 4 days
(19 Reviews)
4.6
aurasky

Hi, I can do this project. I have 7 years experience in VLSI domain

$300 USD in 10 days
(5 Reviews)
4.5
paklancer

Hi, Please see the PMB

$250 USD in 30 days
(0 Reviews)
0.0