Hi,
I have about 17 years experience in FPGA and Embedded Hardware design. I have done logic design for Altera and Xilinx FPGAs. Also have used NIOS II and Microblaze in my designs.
I have not gone through the code but would like to have a better understanding of the setup before that...
1. From my understanding, you are using Master Serial interface for FPGA configuration and using ASMI interface for updating FPGA configuration file?
2. Where is the code for NIOS II stored? Is it external parallel flash or the Serial configuration chip itself is used?
3. Is the NIOS II RAM implemented using Block Memory or External SRAM/SDR/DDR memory used?
Regards
Vinod