Verilog vhdl jobs

I need a Verilog code for both the encryption and decryption of the LEA (Lightweight Encryption Algorithm) cipher, with support for a 128-bit key size. The implementation must also include testbenches for verification purposes. It would be ideal if you have: - Extensive experience with Verilog and digital design. - Knowledge and experience with the LEA cipher. - Prior work involving creating testbenches for hardware verification.

I'm looking for a skilled programmer with experience in Perl and Tcl to convert my existing Perl code into Tcl. The current code is used for analyzing VHDL code through regular expression file analysis. Key Requirements: - Proficiency in both Perl and Tcl - Knowledge of regular expression file analysis We have an AI converted starting version but the whole file conversion is not correct, so probably chekc line by line and testing for comparison is required

I'm new to Verilog and seeking help with the fundamentals, particularly in design coding. My current focus is on understanding module creation, state machines, and testbenches. Ideal skills and experience for the job: - Strong background in Verilog - Experience in teaching or tutoring - Patience and ability to explain complex concepts in simple terms - Good communication skills

please only get back at me if you have huge experience in these things. I am happy to hear from you! Thanks!

Assalam o alaikum, its Muhammad Javed here an electrical & electronics engineer. I am looking for electrical engineers to be a part of my team. I have regular flow of work and already I have a team of professionals and now I am finding more p...professionals to provide me their services in the field of electrical engineers. I need freelancers having firm command over following domains Electric Circuit Design Control System Design Power System Design Image Processing Adaptive Systems Embedded Systems We mostly deal with following software's/hardware's MATLAB/SIMULINK Proteus Multisim PIC Microcontroller Arduino / ESP32 FPGA/VHDL Applicant should be proficient in writing technical FYP reports. Feel free to place your bid if you have expertise in any of ...

I'm looking for a talented VHDL expert who can design a file for the SHA-256 algorithm for an ASIC chip. The primary use case for this algorithm in my project is data encryption. Key Requirements: - Design the SHA-256 algorithm in VHDL - Prioritize processing speed in the chip design - Use a structural VHDL coding style Skills & Experience: - Proven experience in VHDL coding - Deep understanding of the SHA-256 algorithm - Previous work in ASIC chip design - Strong focus on processing speed - Familiarity with structural VHDL coding style

I'm in need of a VHDL expert to design a SPI Master interface and I2C interface. The primary goal of this project is to minimize resource usage without compromising on the functionality and performance of the interfaces. The SPI Master will primarily be interfacing with various sensors. Ideal Skills: - Proficiency in VHDL - Experience with SPI and I2C protocols - Skills in resource optimization in VHDL designs Please provide examples of similar projects you have completed in your bid.

-Using the ARTY A7 35t board -Sending 1ch XADC data -Ethernet will be used to directly connect the board to the PC -The faster the better (at least 1 kHz) -You should use a buffer to prevent data from being pushed out -Data must be transmitted at regular time intervals -You must provide verilog code

I'm looking for a skilled engineer with experience in Digital Signal Processing (DSP) to implement specific functions on a Zedboard using PYNQ. Key Tasks: - Main TASK : help me output wonderin...looking for a skilled engineer with experience in Digital Signal Processing (DSP) to implement specific functions on a Zedboard using PYNQ. Key Tasks: - Main TASK : help me output wondering and correct signal using PYNQ & MATLAB - Familiar with ZYNQ DMA - Implement the Transceiver on Zedboard+AD9361 (I have all the project&code, need to debug) . Ideal Skills and Experience: - Proficiency in Verilog. - Proficiency in Digital Signal Processing. - Hands-on experience with Zedboard and PYNQ. - Knowledge of Communication Synchronization Issues. - Strong problem-solving skills a...

I'm seeking a professional with strong debugging skills and experience with Verilog code on FPGA using Vivado. The task involves identifying and rectifying issues with a specific piece of code. Requirements: - Debugging Verilog code for FPGA - Experience with Vivado - Understanding of communication transmission concepts Project Details: I have a complete set of code and files, but currently, the receive signal is not correct, resulting in incorrect data being received. Ideal Freelancer: - Proficient in Verilog and Vivado - Strong debugging skills - Experience with communication transmission concepts - Chinese speaker preferred

...comprehensive VHDL course . The ideal candidate should have a strong background in VHDL and instructional design, and be able to create engaging and informative content that caters to this target audience. Key responsibilities include: - Designing the course structure in a logical and accessible manner - Creating clear and concise lessons that build upon learners' existing knowledge - Each course outline is available, and is divided into lessons, 10-30 minutes for each lesson, a typical course is composed by 10 lessons. Each lesson is composed by - slides (around 10) - a video 10-20 minutes showing the coding and simulation - the transcript of the lesson - at the end of the course a final project shall be prepared Skills and experience required: - Deep understandi...

I need someone to convert a simple Verilog code into VHDL for FPGA implementation. The design is straightforward, so it doesn't involve intricate logic or multiple modules. Ideal skills and experience include: - Proficiency in Verilog and VHDL - Experience with FPGA design - Ability to understand and convert basic code Please note, this is a simple task and does not require dealing with complex designs or systems.

I'm seeking a Verilog expert to develop RTL code for a low power AES-based 128 bit hardware architecture. The project necessitates the implementation of the AES in CBC (Cipher Block Chaining) mode. Key Requirements: - Expertise in Verilog for RTL code development. - Experience in designing low power hardware architectures. - Understanding of AES encryption and decryption scheme specifically the CBC mode. - Ability to translate design specifications into efficient Verilog code. If you have a strong background in these areas, I would love to hear from you.

I need a VHDL module to control a chain of external shift registers (both input and output). The module needs to be generic so that the number of external shift register bits is configurable via generic parameters. The details as well as a suggested VHDL entity prototype are in the attached PDF.

I'm seeking an expert in VHDL to create a comprehensive course that covers the Basics of VHDL. The course will target beginners in the field, so it should be designed with clear and concise explanations that are easy to follow. Key deliverables: - A series of slides that covers the fundamentals of VHDL in a structured manner - Easy-to-understand examples and exercises that help reinforce the concepts being taught Ideal skills and qualifications: - Proven experience in VHDL and teaching - Ability to simplify complex ideas for beginners - Excellent slide design and presentation skills - Understanding of what makes a course engaging and effective for novice learners Please note, the course should focus solely on the basics of VHDL and avoid delving ...

I'm in need of a skilled FPGA developer who can create a digital clock with the UART data. Here's a breakdown of what the project involves: - **Programming the FPGA**: You should have a strong background in Verilog or VHDL to program FPGA for the digital clock. - **Integrating UART**: You will need to integrate the UART data with the clock for data transmission or reception. - **Implementing 7-Segment Display**: While the specific type of 7-segment display isn't specified, experience with common cathode or anode displays would be beneficial. - **Displaying Time**: Despite the client skipping the preference for time display, it's likely they'd want a 12 or 24-hour format. I'm sure your expertise in this area can accommodate either. Ideal freelan...

I'm looking for an experienced developer to code a timer-based traffic light system on a PYNQ-Z2 board using VHDL. The created system should be able to handle input signals from vehicle sensors for efficient traffic management. you can watch this video on youtube. this is mostly what I want <> Your responsibilities will include: - Writing VHDL code for PYNQ-Z2 board - Incorporating a timer-system for traffic control - Integrating functionality to handle input from vehicle sensors. The ideal candidate should have: - Proficiency in VHDL - Experience with PYNQ-Z2 board - A knack for efficient coding and problem-solving. Familiarity with traffic control systems is a plus, but not a necessity. If you have the skills and experience to meet these requirements

At the start of each round the Game Counter is displayed on the rightmost two digits of the BASYS3 7-segment display. The left two digits are off. A go_i signal is given (pushbutton btnC is pressed) to start the next round. In each round, a random 5-bit binary value, the target number, is selected and displayed on the two leftmost digits and the 5-bit Game Counter (still displayed on the rightmost digits) is set to 1f. After 2 seconds the Game Counter begins to decrement every quarter second. The Game Counter will keep decrementing, rolling under to 1f (31 decimal) after reaching 0. When the stop_i signal is given (pushbutton btnU) the Game Counter stops decrementing. At this point, if the value of the Game Counter matches the target number, then all 4 display digits flash for four seconds...

We have an exisiting design with Lattice FPGA and Verilog to interface to a cameras module with LVDS interface we changed the HW from 4Bit to 8Bit support. Now we need to change the Verlilog as well. see allso file attached

I am on the hunt for a keen RTL Designer who is highly proficient in VHDL and Verilog. Your main task will be creating VHDL/Verilog code for a thermal sensor-related project. The work will involve: - Developing VHDL/Verilog codes designed specifically for Xilinx FPGAs. - Accommodating advanced code complexities, with a focus on custom processors or complex IP cores. Skills and Experience: - Well-versed in digital design and RTL coding - Extensive experience in VHDL/Verilog - Deep knowledge of Xilinx FPGAs - Experience in implementing advanced, custom processors, and complex cores Please, your bid should reflect your experience level and capability to handle this advanced task. Be prepared to share previous relevant work examples...

I'm looking for an experienced FPGA expert who can help me with a project that involves developing the architecture, implementing the logic, and ensuring that the functionality is correct. The main goals of this project are data processing, signal processing, and hardware acceleration. While I did not specify a language preference, experience with languages like VHDL, Verilog, and SystemVerilog would be a plus. Key requirements for this project include: - Develop the FPGA architecture - Implement the logic for data and signal processing - Ensure the FPGA functions as intended for hardware acceleration Please apply if you have a strong background in FPGA design and implementation, and are able to work with the specified languages.

Troubleshooting: I will troubleshoot the problem, focusing on the section of the code where the input is processed and the subsequent actions are determined. Code Modification: I will modify the VHDL code to ensure that the program continues to run correctly after a player inputs a number. Testing and Verification: I will rigorously test the updated code using the TEST BENCH to verify that the issue is resolved and the program runs smoothly from slot 5 onwards. Revisions: If any additional issues arise or further adjustments are needed, I will promptly make the necessary revisions to ensure complete satisfaction.

I'm in need of a VHDL expert who can debug and correct my existing code. The goal of the code is to print only numbers on the command screen. Key Requirements: - Debug and correct existing VHDL code. - Ensure the output is only numerical. - Open to suggestions on how to improve the existing code. Ideal Skills: - Proficient in VHDL. - Prior experience in debugging and modifying VHDL code. - Familiarity with interfacing VHDL code with external hardware. - Strong problem-solving skills.

...develop high-quality content for our website, LinkedIn page, blog, and short courses. The focus of the content will be on FPGA (Field-Programmable Gate Array) design, VHDL, and related topics. The goal is to provide valuable educational resources to our audience. Key Responsibilities: - Develop engaging and informative content for various platforms - Increase brand visibility and credibility in the FPGA community - Provide educational resources that support our services and courses Ideal Skills: - Engaging writing style tailored to the target audience (electronic engineers, FPGA designers, etc.) - In-depth knowledge of FPGA design, VHDL, and related technologies - Ability to explain complex technical concepts in a clear and understandable manner - Understanding of SEO b...

Assalam o alaikum, I am looking for electrical engineers from Pakistan to assist me in multiple tasks on long term basis. Applicant must be proficient in following: Arduino Pic Microcontroller Raspberry Pi FPGA (VHDL) Multisim Proteus PCB Design TinkerCAD MATLAB (Control System Design) Freelancers should have good command in technical report writing.

...seeking an experienced FPGA developer to facilitate a data transfer without any processing: The data arrives via a TCP/IP connection and has to be copied into buffers in DRAM by a Linux application on the Zynq. The Programmable Logic (PL) then takes that data from DRAM and feeds it into a FIFO. Several buffers in round-robin fashion need to be used. Key Elements of the Project: - Programming in VHDL/Verilog - Proficiency with Xilinx Zynq-7000 SoC - Experience with transferring data from the Zynq ARM core to the PL via DRAM at high speed The completion of the task will require a thorough understanding of the Zynq-7000 architecture and cache coherency as well as the Zynq AXI interfaces. The ideal freelancer for this job should have previous experience in dealing with simi...

I'm seeking a competent Verilog/VHDL developer to create an image processor for scientific imaging. The primary focus of the processor is noise removal, specifically salt and pepper noise. Key Requirements: - Noise Removal: The processor must effectively remove salt and pepper noise from the input images. This is crucial for the intended application in scientific imaging. - Real-time Processing: The design should ideally support real-time processing for seamless image enhancement. - Deadline: This is an urgent project with a tight 2-3 day deadline. Punctuality is paramount. Ideal Skills and Experience: - Proficiency in Verilog/VHDL: Extensive experience in Verilog/VHDL development is necessary to tackle this project effectively. - Image Pro...

Hi, Take a look at this project: ...should have digital blocks just like the above and then synthesized and integrated with the analog components like comparators, buffers, etc, basically very similar to the above project. Or 2) Just reproduce the above GitHub project such that it is less complicated but it should be 12 bit like before. I should be able to understand it. I tried it myself but there were some problems like in verilog to spice conversation and some spice files giving errors and most simulation getting stuck because it takes too much time 1) or 2) you may do any one whichever seems possible. Note that it is for my self learning purposes and any help regarding reproducing it or understanding it or learning to simulate it will be beneficial for me and I will pay ac...

Job Description: We are searching for an exceptional RTL Design Specialist specializing in ASIC/VLSI to play a ...optimized for LLM training and benchmarking. Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes. Job Requirements: BS or MS degree in Electrical Engineering or a related field. 3-5 years of proven experience in hardware design development. RTL design specialization in ASIC/VLSI. Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC. Expertise in scripting, front-end, and verification workflows, and integrations within the hardware design environment. Exceptional problem-solving, communication, and collaborative skills. Familiarity with Synopsys/Cadence or o...

...Responsibilities: - Hardware design: You'll be responsible for creating and implementing hardware designs, including system architecture, chip layout, and integration. - Enhancing LLMs: Your primary focus will be on optimizing and enhancing the LLMs using your ASIC/VLSI, and Verilog/SystemVerilog/VHDL/SystemC expertise. Ideal Skills and Experience: - A strong background in Electrical Engineering, with a Bachelor's or Master's degree. - 3-5 years of experience in the field of ASIC/VLSI design. - Proficiency in Verilog/SystemVerilog, VHDL, and SystemC. - Previous experience in enhancing LLMs would be a strong advantage. This role is ideal for someone with a keen interest in hardware design and a passion for creating innovative solutions. If you...

I'm seeking intermediate-level electrical engineers for a long-term project. The ideal candidate should have a good grasp of circuit design, power system analysis, control system development, as well as experience in PCB design, Arduino, FPGA, Raspberry Pi, and Verilog/VHDL. Key responsibilities: - Circuit design, power system analysis, and control system development - Proficiency in MATLAB/Simulink for simulations and modeling - Expertise in EAGLE or Altium for PCB design - Knowledge of Verilog/VHDL for FPGA development This role might be a great fit for someone with an academic background in electrical engineering, a few years of industry experience, and a solid portfolio of relevant projects. The work is ongoing and offers a variety of tasks, so adapt...

Seeking a proficient RTL design engineer to assist with a block-level design project. Your daily tasks will include Linting, CDC analysis, and Synthesis. Expertise is required in Verilog, the preferred hardware description language for this assignment. Required Skills and Experience: - Exceptional competence in RTL design - Proven experience in Linting, CDC analysis, and Synthesis - Proficiency in Verilog - Experience in block-level design preferred I look forward to collaborating with an engineer who will contribute valuable insight and expertise towards achieving the project objectives.

...Large-Scale Integration) architecture that is designed to classify Atrial Fibrillation for wearable devices. This ambitious project requires specialised expertise and precise execution. Key Tasks: - The design of a Low-Power, DNN-Based VLSI architecture, which is yet to be initiated. - Create a Full Custom VLSI that is suited for classifying Atrial Fibrillation. Ideal Skills and Experience: -Verilog. -FPGA. - Relevant experience and extensive knowledge of designing Full Custom VLSI architectures. - Proven expertise in VLSI architectures and their relation to wearable device technology. - Firm understanding of Atrial Fibrillation classification. - Familiarity with power optimisation in VLSI designs would be an advantage, although not a requirement. Candidates who can apply th...

I'm in need of a Verilog expert proficient with Quartus Prime Toolchain. Key Requirements: - Professional with Verilog: Need someone experienced in designing digital circuits and implementing specific functionalities using Verilog. - Proficiency with Quartus Prime: Familiarity with the Quartus Prime Toolchain is a must. I need to design, simulate, implement and test a digital circuit using the Quartus Prime toolchain as per the specifications I will provide and demonstrate the workflow when using the Verilog HDL to construct a design for a physical Field Programmable Gate Array (FPGA) target. Please apply if you have the required expertise. No teams or companies please.

We are looking for an experienced freelancer to create a custom DMA firmware using this simple guide : The guide provides detailed instructions, but I lack the time to complete it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone pr...it myself. The project will be executed on a Squirrel 35t board and should not take more than 3-4 hours for someone proficient. **Tasks:** - Configure and customize firmware based on pcileech-fpga - Use Vivado for development - Emulate TLP and configure the configuration space **Required Skills:** - FPGA design and programming - Experience with Vivado (Xilinx) - DMA firmware development - Verilog/VHDL programming - Debugging and testing embedded systems

I am looking for an experienced Verilog developer who can work on my Verilo HDL project. Design a digital circuit for a fruit sorter based on following specification. Develop the block diagram (consists of datapath and control units) and the ASMD chart. Assume that there is a 1-bit RESET signal to reset the circuit and it is asynchronous and active low. In addition, there is a 1-bit CLOCK as the clock. The circuit will start the operation when a 1-bit input signal START is asserted. A fruit detector provides a 1-bit input FRUIT that becomes 1 for one clock cycle if banana is detected and the FRUIT signal will be 1 for two clock cycles if orange is detected. There are 2 different outputs which are OUT1 and OUT2 that will be 1 for one clock cycle for the type of frui...

...into Verilog and run on FPGA device using HLS Vitis. The existing project has: - Edge detection capabilities - Image segmentation capabilities The primary goal of this project is not to enhance or alter the images, but to convert the existing codebase from C++ to Verilog, utilizing HLS Vitis. With your expertise: - Maintain the integrity of the current functionalities during conversion - Reframe the C++ code to Verilog language ensuring a seamless running on an FPGA device. The successful bidder should have significant experience with Verilog, C++, and HLS Vitis, as well as a good understanding of Image Processing algorithms, especially Edge Detection and Image Segmentation. The final output of the conversion should result in an image file product. The d...

I'm currently seeking an individual who is not only proficient in VHDL coding but also in Quartus design implementation. Key Responsibilities: - Work on specific tasks related to VHDL coding - Implement design using Quartus While the overall aim of the project and the timeline aren't specified yet, I am eager to work with someone who is flexible and can adapt as per project needs. The ideal candidate for this role should be based in Pakistan, knowledgeable in FPGA programming, dependable, efficient, and proactive when it comes to troubleshooting and problem-solving.

Greetings, We are assembling a dynamic team and currently seeking 4-5 proficient Electrical Engineers to join us for a long-term collaboration. This opportunity is ideal for individuals with expertise in electronics, power systems, and communication systems. Key Requirements: - Strong command over MATLAB for data analysis, simulation, and modeling. - Proficiency in VHDL and Verilog for hardware description and digital circuit design. - Experience with multisim or similar simulation software for circuit analysis and design verification. This collaboration offers an exciting chance to work on diverse projects spanning electronics, power systems, and communication systems. We are committed to fostering a collaborative environment that encourages innovation and professional gr...

I need verilog code,testbench and simulation for this duty : Design a vector processing system that performs dot product of two vectors kept in the memory. The length of the vector is given as an input and at each clock cycle one element from each vector is multiplied and added. At the end of the processing a valid signal will be raised along with the result. Elements of the vectors are 8-bit unsigned vectors.

I'm seeking a VHDL expert for a college project revolving around basic logic gates. The project involves primarily circuit design, with an emphasis on the following: - The project is centred around basic logic gates (AND, OR, NOT) - so the complexity level is relatively beginner-friendly - A key part of this task is the delivery of comprehensive project documentation along with the circuit design. This will help me understand the design process and the logic behind it. If you have experience in VHDL and can deliver both the circuit design and documentation, I'd love to hear from you. Please include details of similar projects you've worked on, as well as your experience level with VHDL.

Im working on a c++ image processing project , and i need to convert my C++ code to Verilog using HLS vitis , then implement it to run on Ultra96v2 Xilinx FPGA board .

I'm in need of skilled programmers to develop interfaces for my Place and Route EDA flows. The ideal candidate will have experience in the following: - Proficiency in Python and/or C++ - Familiarity with VHDL, Verilog, and SystemVerilog - Experience in file input generation - Strong file parsing capabilities - Ability to manage EDA flows using TCL The interfaces need to be able to handle the entire EDA flow, from file input generation to error reporting. Experience in developing similar interfaces will be a big advantage. Please include relevant work samples in your bid.

I'm in urgent need of skilled VHDL/Quartus professionals from Pakistan for a project. I will clarify the specifics once a mutual understanding and agreement is reached. Ideal skills for the job include: - Proficiency in VHDL/Quartus - Ability to design, troubleshoot and optimize digital circuits - Ability to work independently or with minimal supervision - Excellent communication skills to effectively explain intricate concepts or problems Experience level can range from beginner to expert. The expectation, however, is the ability to deliver quality work within the stipulated time-frame.

I am currently working on a traffic light project and I need the expertise of a VHDL programming guru. Someone who has had previous experience programming the FPGA DEO Nano development board would be a perfect fit, as that's what I am specifically working with. I am using VHDL to code for the EP4CE22F17C6N board. The base of my project, using a state machine, has already been created. As far as the hardware end of things, I've already prepared the circuit diagram and have started with LED lights and toggle switches. But I do need to make some changes in it as the requirement in order to make it more complex for that I need someone who can do the following additions or changes in the project that I have attached in my zip folder to work exactly as described in the ...

Stepper motor controller in FPGA which generates pulses according to command. verilog code

hello, I have a project and I'm stuck at some point, please see the specifications in the zip it's for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering...for tomorrow morning budget:20$ language:french,arabic actually no need for much because I have already done rendering 1 and rendering 2 of the project, now for rendering 3, I just need to modify the block diagrams, the truth table, the state graph and the memory map (which are all done during rendering 1) according to the modifications requested by the workbook. load... We don't need coding in vhdl, just make the modifications on rendering 1 according to the instructions for rendering 3 if ever we can do a 10 minute meeting to e...

I'm seeking an experienced trainer for Spyglass tool, with a concentration on Lint and CDC (Clock Domain Crossing). As beginners in Spyglass and proficient in Verilog, we primarily aim to identify and fix coding errors through this training. Ideal Skills and Experience: - Strong knowledge of Lint and CDC in Spyglass tool - Demonstrated experience in coding and debugging in Verilog - Excellent training skills - Ability to create and simplify complex concepts for beginners.

...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...

...programmer, who possesses proficiency in both Verilog and Vivado, to construct and operate a user-friendly program for my FPGA board. The selected FPGA board is from the Xilinx Artix-7 family (part: xc7a100tcsg324-1). The program’s main responsibility will be to feature a rudimentary vending machine program with the following specifications: - Two component spaces which will each hold a distinct item. - A simplified interface featuring two push buttons as part of a keypad. - A capable card reader to handle seamless payment processing. - A clear 3 digit display that relays instructions and alerts to the user. An ideal candidate for this project should have extensive experience working with Artix-7 FPGA boards and demonstrate a clear understanding of Verilog and V...