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    289 project vlsi design jobs found, pricing in ZAR

    Build a basic building block of the Carry-Skip adder and test it for functionality in LTSpice. Description is in: [url removed, login to view] Reference: [url removed, login to view]

    R293 (Avg Bid)
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    8 bids

    Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool)

    R11765 (Avg Bid)
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    10 bids

    ... SBL TECHNOLOGIES is a proven semiconductor and embedded design house in India, with deep focus and network in Indian Defence and production agencies. Setup by an experienced team of engineers from the industry to carry-out research, design, development and manufacturing in the field of VLSI and Embedded systems. PCB services from the initial stage

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    20 bids

    i need 15 pages presentation on speed optimization techniques in VLSI.

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    7 bids

    VLSI developer expertise enhanced in optimization concepts are required

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    8 bids

    ...need a project suggestion for a masters project in VLSI testing and verification using Synopsis EDA tools for sequential circuits, because I have to submit a project proposal. Once a project suggestion seems acceptable, I will need help in finishing the project with desired outputs and compare the same with FPGA implementation. By bid for project...

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    11 bids

    I need some one has background about VLSI

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    8 bids

    I need help in my company project (more details will be share with shortlisted candidate) You have to be very good in MIPS assembly language RTL, verilog, and basics VLSI technology to be shortlist you have to solve one MIPS Asm. question (attached below) as soon as possible.

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    5 bids

    I am going to do my research so I need useful research ideas in electronics, electrical, IT domains and those who have research ideas in VLSI , Embedded systems, Finfet technology, Drones bid me.

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    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

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    6 bids

    Looking for project topics in VLSI testing and verification using Synopsis EDA tools and TETRAMAX for sequential circuits. Once a topic has been selected, I would need help in finishing the project with desired outputs. Finally, I would also need an explanation of the functioning after completing the project.

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    10 bids

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    R265 (Avg Bid)
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    4 bids

    I need you to develop some software for me. I would like this software to be developed for Windows using Python. floor planning of vlsi module , I have to optimise it using Patrical swarm algorithm , need gui for it It requires 1. formation of model ,i.e placement of [url removed, login to view] with a big block 2. if there are 4 block within a big block then there

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    4 bids

    An efficient Glitch power reduction using sequential clock gating in VLSI circuits

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    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

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    3 bids

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

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    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

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    5 bids
    VLSI technologia Ended
    VERIFIED

    I need you to write a research article . About VLSI technologia

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    11 bids

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    R2148 (Avg Bid)
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    7 bids

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    R1561 (Avg Bid)
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    2 bids